In recent years there has been substantial growth of mobile communications devices, primarily cellular telephones and personal digital assistants. These devices demand ever-increasing power added efficiency (PAE) to achieve long battery life in support of increased talk times. The transmitting amplifiers in these devices have in recent years, migrated to gallium arsenide (GaAs) heterojunction bipolar transistors (HBT) technology. One advantage HBTs provide is the ability to effect high power densities across small areas. Compound semiconductors GaAs and indium phosphide (InP) based binary, ternary or quaternary alloys work well in this regard and may provide an advantage over the silicon-based devices found in most applications. However, one disadvantage of compound semiconductors is the relatively poor thermal conductivity in comparison to silicon, causing self-heating of the individual devices that may result in unstable operation.
In addition to the reduced battery power requirements, the size of cellular phones and the corresponding circuitry within has continually decreased. However, the transmitting power requirements of the devices remain the same in order to maintain clear communication signals. The reduced circuitry size together with transmitting power requirements produce increased power densities, which, when coupled with the problem of heat removal, result in higher operational temperatures for these devices and further degrade the long-term reliability of the device.
To maintain the performance of the transistor for large power applications, typically the transistor is divided into many small transistors electrically tied together in parallel. However, thermal stability becomes more challenging with a greater number of transistors and associated transistor fingers used to input to signals to and output signals from the transistor. Specifically, the devices near the center of an array of transistors tend to run at a higher temperature than those at the edge of the array, leading to poor overall thermal stability. This issue is commonly addressed in power amplifiers implemented with bipolar transistor technology by the application of distributed ballast resistors as reducing the overall thermal resistance of the transistor can also improve matters of thermal stability.
The process of making an HBT starts the depositing of epitaxial crystalline layers that form the active material of the individual HBT. The follow-on processing steps delineate each of the transistors by masking and etching away transistor material from the area of the wafer. This provides a method of electrically contacting the collector, base, and emitter layers of the HBT. The routing of signals through electrodes across the amplifier and the insulating material are done to minimize capacitances and inductances.
One of the problems with the current technology, however, is the inefficiency of the device layout and in the use of valuable epitaxial transistor material as a substrate base for interconnects, electrodes and various other passive elements, which results in inefficient use of die area. The interconnects are patterned on material that might otherwise provide additional transistors, thereby allowing the more valuable wafer area to be put to better use. It would thus be advantageous to provide a reduced size device that reduces manufacturing costs by the realization of more die from a given wafer and a method of producing such a device. It would also be of advantage to remove the heat from the active device efficiently so that device operation is not impaired, allow for a more stable environment for radio-frequency (xe2x80x9cRFxe2x80x9d) signal amplification, and provide a more efficient and compact method to distribute dc bias among the many transistor cells.
In one embodiment, the semiconductor amplifier comprises at least one amplifier cell including a plurality of transistors cells on a substrate and at least one collector strap that forms an air bridge over a set of the transistors. A contact pad may provide a signal output for collectors of the transistors, with the collector strap making electrical connections between the collectors and the contact pad.
An adjacent pair of transistors may share collector contact material and a subcollector. One bridge of the collector strap may be connected with collector contact material of a first adjacent pair of transistors and a neighboring second adjacent pair of transistors. The bridge of the collector strap may span one of the transistors of the first adjacent pair of transistors and one of the transistors of the second adjacent pair of transistors.
In a second embodiment, the amplifier may include a ground disposed on a back side of the substrate with the amplifier cell being arranged on a front side of the substrate, a plurality of electrodes electrically connected with emitters of the transistors, and a plurality of ground vias through the substrate. The ground vias may be connected with the electrodes and allow at least one of direct (DC) and radio-frequency (RF) current flow to the grounded conductive layer. The emitters of a neighboring pair of transistors may be connected through one of the electrodes to a corresponding via. The transistors may be aligned in rows and the vias may be adjacent to every other row of the transistors.
In a third embodiment, the amplifier may include a plurality of resistive elements connected with bases of the transistors and at least one base strap connecting the resistive elements and forming an air bridge over the resistive elements. Adjacent pairs of transistors may share one resistive element. Capacitors may be connected with the bases of the transistors and a symmetrical interstage feed, which is configured to receive an input signal and configured to supply the input signal to the capacitors. In addition, a bias circuit may be added to adjust the transistors DC current.